As an ASIC Layout Engineer (m/f/diverse) for AESS (Advanced Electronics & Semiconductor Solutions), you will be responsible for the top-level integration of analog and mixed-signal ICs. You will drive the layout development process, ensuring robust, DRC-compliant designs with optimal area utilization. You will collaborate closely with analog circuit designers and other layout engineers to deliver high-quality silicon.
Key Responsibilities
- Drive the top-level layout integration of analog/mixed-signal chips (analog on top)
- Define toplevel floorplan, padframe design and bonding diagrams in coordination with other domains
- Coordinate with other layouters to define floorplans according to the chip top level
- Generate and integrate analog layouts at block and chip level
- Perform pin placement, parasitic extraction, and layout optimization
- Ensure compliance with DRC, LVS, and support tape-out activities
- Collaborate with design engineers to meet speed, area, power, DFM, ESD, and EMC requirements