Job Details:

Job Description:

In this position, the candidate will be part of a team implementing ASIC designs for Integrated/Discrete Graphics and AI SoCs on leading edge process technology and EDA tools.

* The team is responsible for all SoC level physical design and optimization flows ranging from Floor-planning, Clocking, Synthesis through GDS and parallel verification aspects such as Static Timing Analysis, Formal Verification, EM/IR/PDN verification, Quality Assurance, Layout Verification etc.

* The ideal candidate will have the skills and experience to lead SoC level floorplan development and convergence through a product development cycle. 

* The candidate must independently drive efforts to meet density, timing and modularity requirements across design hierarchies while utilizing knowledge of architecture, data flow and process requirements.

* Responsibilities may also include defining design requirements such as frequency, operating voltages, power, etc. to achieve optimized designs on new technologies, processes and architectures.

* The candidate will be required to work closely with the rest of the project team members to resolve issues which arise during the design cycle and take the key learnings into the next product cycle.

* Good leadership and communication skills are necessary due to the nature of the work, size and complexity of the products and the size of the team.

Qualifications:

Minimum Qualifications:

Minimum qualifications are required to be initially considered for this position. Requirements listed would be obtained through a combination of industry-relevant job experience, internship experience and or schoolwork/classes/research.

• Bachelor’s in Electrical/Computer Engineering with 9+ years relevant work experience, or Master's in Electrical/Computer Engineering with 6+ years relevant work experience
• Experience in: Logic Design, VLSI/ASIC Design, Computer Architecture
• Current Industry Experience in one or more ASIC style design flows – floorplanning, clock construction, synthesis, place and route, static timing analysis, layout verification
• Experience with Unix/Linux, Perl and TCL in order to implement useable, flexible cshell/perl/tcl programs that automate tool/flow methodologies

Preferred Qualifications:

Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates

• Preferred Experience in SoC integration methodologies including fullchip design planning and integration of a variety of blocks into an SoC design
• Preferred Knowledge of clock construction methodology, bus planning, timing budgeting and repeater optimization

Job Type:

Experienced Hire

Shift:

Shift 1 (India)

Primary Location:

India, Bangalore

Additional Locations:

Business group:

Intel makes possible the most amazing experiences of the future. You may know us for our processors. But we do so much more. Intel invents at the boundaries of technology to make amazing experiences possible for business and society, and for every person on Earth. Harnessing the capability of the cloud, the ubiquity of the Internet of Things, the latest advances in memory and programmable solutions, and the promise of always-on 5G connectivity, Intel is disrupting industries and solving global challenges. Leading on policy, diversity, inclusion, education and sustainability, we create value for our stockholders, customers, and society.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

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ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.