Job Details:

Job Description:

This position is within the Design Technology Platform (DTP) organization of Intel Foundry.

At Intel, Design Technology Platform is one of the key pillars enabling Intel to deliver winning products in the marketplace. Your work will directly enable design teams to get to market faster with leadership products on innovative technologies. As part of the DTP Process Design Kit (PDK) group, you will join a highly motivated team of talented engineers solving challenging technical problems, enabling PDKs for Intel's most advanced process technologies, and drive PDKs towards industry standard methods and ease of use for the end customers.

The job requires partnering and leveraging domain experts across various areas of Technology Development, EDA vendors, and product design teams to develop and deliver high quality technology collaterals, models, and enablement of EDA tools.

Runset Development:

Runset Development team within this organization is to develop physical layout verification software (DRC, LVS, RC extraction) and support the latest Intel technologies and microprocessor designs.
Develop runset using industry standard EDA tools (Synopsys ICV, Siemens/Mentor Calibre, and Cadence Pegasus).
Coordinate development of technology features, develop QA plans, and drive test-cases development working with relevant stakeholders.
Support PDK development and Intel design teams to debug and enhance runset quality and enhance runtime and usability of the runset.

PERC ESD Verification Development:

Develop ESD protection verification on emerging PERC verification tool of major EDAs (Calibre, ICV, Pegasus).
Understand circuit topology and various ESD protection schemes, and implementing it in verification runset.
Understand circuit parasitic element (resistance and capacitance), and it's extraction and verification in PERC.
Develop the state-of-art PERC ESD verification workflow.

Extraction Development:

Understand and model parasitic related to the interconnects.
Work with multiple EDA companies to co-develop extraction solutions.
Develop new extraction techniques to address upcoming technology features not yet handled in existing industry extraction tools and validates EDA solutions against models and measured data.
Extraction runset and flow development using popular extraction solutions (StarRC, Quantus, xACT)
Work with various solvers (e.g. Raphael, HFSS, Fast Henry, Quick Cap, university-developed tools) and popular 2D and 3D electromagnetic packages.

"Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to our staffing team at malaysia.staffing@intel.com."

Qualifications:

The candidate must possess minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your schoolwork class research and or relevant previous job and or internship experiences.

Minimum Qualifications:

Bachelor/Master in Electrical / Electronics Engineering, Computer Engineering, Computer Science, or other related Electrical Scientific STEM field.
6+ months of work or educational experience in at least one of the following areas:
Unix/Linux operating system
Programming or scripting in at least one of: C++, Python, Ruby, Perl, Tcl, SKILL
CMOS device physics, process technology and design rules

Preferred Qualifications:

Experience with working in software repository management tools like Git
Knowledge of DRC/LVS/Extraction runsets
Knowledge in semiconductor device physics, models, parasitic extraction, and technology scaling
Familiarity with VLSI design process, reliability verification, ESD concepts, standard cell library, and memory architectures
Familiarity with custom layout design of analog, RF, or digital circuits on advanced process technology nodes
Working knowledge of EDA tools (Synopsys ICV, Siemens/Mentor Calibre, Cadence Pegasus, Virtuoso or Custom Compiler, Cadence Innovus, Synopsys Fusion Compiler or Siemens Aprisa tools)

#designenablement

Job Type:

College Grad

Shift:

Shift 1 (Malaysia)

Primary Location:

Malaysia, Penang

Additional Locations:

Business group:

Intel Foundry strives to make every facet of semiconductor manufacturing state-of-the-art while delighting our customers -- from delivering cutting-edge silicon process and packaging technology leadership for the AI era, enabling our customers to design leadership products, global manufacturing scale and supply chain, through the continuous yield improvements to advanced packaging all the way to final test and assembly. We ensure our foundry customers' products receive our utmost focus in terms of service, technology enablement and capacity commitments. Employees in the Foundry Technology Manufacturing are part of a worldwide factory network that designs, develops, manufactures, and assembly/test packages the compute devices to improve the lives of every person on Earth.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

Graduate Talent (PDK Development Engineer)

Job Description