Job Details:
Job Description:
Performs functional logic verification of an integrated SoC to ensure design will meet specifications. Defines and develops scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to microarchitecture specifications. Executes verification plans and defines and runs emulation and system simulation models to verify the design, analyze power and performance, and uncover bugs. Replicates, root causes, and debugs issues in the presilicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates and communicates with SoC architects, microarchitects, full chip architects, RTL developers, postsilicon, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Incorporates and executes security activities within test plans, including regression and debug tests, to ensure security coverage. Maintains and improves existing functional verification infrastructure and methodology. Absorbs learning from postsilicon on the quality of validation done during presilicon development, updates test plan for missing coverages, and proliferates to future products.
Qualifications:
Minimum Qualifications:
Bachelor's degree in electrical engineering or computer engineering with 4 to 9 years of experience or a master's degree in electrical engineering or computer engineering.3+ years of experience in 5 or more of the following:
Test Bench bring-up at SoC and strong programming skills in System Verilog, OVM and UVM.
Test Plan development experience.
Enabling regressions, maintaining QoV (quality of validation) with good functional/code/other coverage metrics.
Familiarity with both simulation and emulation environments.
Strong CPU/GPU architecture understanding.
RTL Debugging module level or soc level system simulation failures.
Building emulation models, enabling content.
Monitoring and improve existing simulation environments and simulation efficiency.
Preferred Qualifications:
Experience with DFD (Design for Debug) component i.e. VISA DTF, TFB will be a plus.
Job Type:
Experienced Hire
Shift:
Shift 1 (India)
Primary Location:
India, Bangalore
Additional Locations:
Business group:
As a member of the Chief Technology Office, Artificial Intelligence, and Network and Edge Group (CTO AI NEX), you will be committed to strategically penetrating the AI market by delivering disruptive and transformative solutions. Your focus will be on leveraging technology innovation and incubation to drive commercial success, ensuring that advancements create significant value. The team is dedicated to driving the software-defined transformation of the world's networks profitably, setting new standards for efficiency and connectivity. Through these priorities, you aim to lead the way in technological evolution and redefine the future of global networks.
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
N/A
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
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