About Intel Central Engineering Group

Intel's Central Engineering Group (CEG) is committed to transforming engineering processes while expanding market reach through internal product development and external ASIC design services. Three interconnected pillars drive CEG's mission to enhance Intel's engineering execution and market opportunities, all guided by a data-driven approach that ensures scalable impact.

Position Overview

We are seeking aSeniorMixed Signal Verification Engineer specializing in clock generator IP verification to ensure functional correctness of PLL/FLL designs. This role combines digital verificationexpertisewith mixed-signal validation capabilities, requiring collaboration across architecture, RTL development, and analog design teams to deliver high-quality clock generation solutions.

Key Responsibilities

Clock Generator IP Verification

• Perform comprehensive functional verification of clock generator IPs including PLL/FLL to ensure designs meet specification requirements
• Proactively and independently develop test benches, verification environments, tests, and checkers/assertions ensuring coverage compliance with IP microarchitecture specifications
• Lead Mixed Signal Validation (MSV) activities by running AMS simulations and collaborating cross-functionally toidentify, root-cause, and resolve schematic bugs

Verification Environment Development & Debug

• Replicate, root cause, and debug complex issues in the pre-silicon environment using systematic debuggingmethodology
• Maintain and improve existing functional verification infrastructure andmethodologyfor multiple generations of IP test benches
• Document comprehensive test plans and drive technical reviews with design teams

Cross-Functional Collaboration & Development

• Collaborate with architects, RTL developers, and analog schematic owners to improve verification of architectural and microarchitectural features
• Participate actively in the definition of architecture and microarchitecture features of the IP being designed
• Participate in RTL development activities and contribute to design optimization

Specialized Knowledge

• Understanding of mixed-signal design principles and AMS simulation techniques
• Knowledge of clock generation architectures and timing analysis
• Familiarity with analog verification methodologies and tools
• Experience with clock domain crossing verification and analysis

Core Competencies

• Strong analytical and problem-solving skills for complex verification challenges
• Ability to work independently while collaborating effectively across multiple teams
• Excellent documentation and communication skills for technical reviews

The Minimum qualificationsare required tobe considered for this position. Minimum qualifications listed below would be obtained through a combination of industry relevant job experience, internship experience and / or schoolwork/classes/research. The preferred qualifications are in addition to theminimumrequirements and are considered a plus factor inidentifyingtop candidates.

Minimum Qualifications

• Bachelor'sdegree in Electronics/Electrical/Computer Engineering 
• 3+ years of experience in Design Verification and Validation methodologies with UVM,SystemVerilog, and industry-standard EDA tools
• 3+ yearsofexperience in scripting languages such as Python and Perl

Preferred Qualifications

• Post graduatedegree inElectronics/Electrical/Computer Engineering 
• Experience withdebug methodologies
• Experience with RTL development and design implementation
• Experience working on PLL/FLL or SoC clocking architectures and verification

What We Offer

• Opportunity to work oncutting-edgeclock generation technologies and mixed-signal verification
• Collaboration with world-class engineers in architecture, design, and verification
• Access to advanced EDA tools and verification infrastructure
• Professional development in mixed-signal verification and clock design
• Direct impact on Intel's IP portfolio and engineering execution excellence