Job responsibilities:
8+ Years of relevant Logic Verification experience
Able to lead and Develop test plans, tests and verification infrastructure for a complex IP/Sub-System or lead major deliverables for SoC
Create verification environment using UVM methodology
Create reusable bus functional models, monitors, checkers and scoreboards
Drive functional coverage driven verification closure.
Work with architects, designers, and post-silicon teams
Hands-on contributions to SVA development like coding, porting and maintaining System Verilog Assertions
Development of tools for Design and Verification support
Debug failures and root-cause it by interacting with other teams/groups Etc.
Skills Required/Preferred:
- Software Skills Required:
Proficiency in Computer Science fundamentals – object oriented design, data structures, algorithms, design, problem solving, and complexity analysis
Basic knowledge of with c, c++, SystemC, perl, python, tcl, shell is preferable
- Functional Verification:
Unit/Sub-system/SOC level verification experience
Experience in leading verification closure of complex IP/SOC for at least one project
Exposure to industry standard verification tools for simulation and debug
RTL & Gate Level Simulations
Proficiency in Verilog, System Verilog & Assertions , UVM and Functional Coverage
Exposure to Verification Fundamentals
Verification Automation using scripts like Perl,shell,tcl/tk
Good debugging and problem solving skills.
Good communication skills and ability, desire to work as a team player
Exposure to Analog verification will additional plus point
-Digital design Concepts
- CMOS VLSI, Digital Circuits
- Knowledge on Memory (preferred)
(SRAM/DRAM/ROM/Flash) Circuits/Logic
- Preferred exposure
- NCSIM, Xcellium, IMC, IEV, Verdi, Jasper, VS Formal
- Cadence Schematic and layout environment