We are seeking a highly skilled and experienced System Validation Architect specializing in UFS/eMMC. This role bridges customer engineering, system validation, and eMMC/UFS spec compliance.
As the key player of system validation, expected to own the validation strategy, debug and triage system-level issues.
Key Responsibilities:
- System-Level Validation Strategy and development:
- Architect and define test strategies for system-level UFS/eMMC validation, covering protocol compliance, performance, power, latency, interoperability and FW algorithm validation.
- Develop and automate validation plans aligned with JEDEC/UFS/UFSHCI/UFS-MIPI/eMMC specifications
- Cross-Functional Collaboration:
- Work with firmware, hardware, ASIC, and software teams to align system validation with product development cycles.
- Debug and Automation:
- Use advanced tools (e.g., protocol analyzers, oscilloscopes, logic analyzers) for deep-dive debugging.
- Support and enhance test automation infrastructure for scalable validation.