This is a "full-stack" ML systems role for a senior individual contributor and technical architect. You will be responsible for designing the complete ML ecosystem for our edge devices, from the cloud-native MLOps platform down to the bare-metal model optimization.
This unique role blends three key domains:
MLOps & Data: You will architect the entire data lifecycle, including our CI/CD pipelines, data-labeling loops, and on-device monitoring.
Agentic & Edge AI: You will lead the design of autonomous agents that run on our edge devices, using domain knowledge in log analysis and computer vision.
Systems & Hardware: You will be the "hardware-aware" expert, bridging our ML software with our silicon team to ensure our models are hyper-optimized for our custom NPU.
You are the engineer who will not only build our ML platform but also design the intelligent agents it deploys and ensure they run faster and more securely than anyone else's.
Key Responsibilities
Architecture & Leadership:
Act as a senior individual contributor, leading by example with hands-on coding, design, and analysis across the entire ML stack.
Define the end-to-end architecture for our MLOps, agentic AI, and model optimization strategy.
MLOps & Data Platform:
Design and implement our data processing and versioning pipelines, ensuring data integrity and traceability.
Build the infrastructure for our Human-in-the-Loop (HITL) and AI-in-the-Loop (Active Learning) data labeling systems to continuously improve our datasets.
Develop a comprehensive, lightweight on-device monitoring system to track not just operational metrics but also inference quality and concept drift.
Agentic & Edge Development:
Design and development of autonomous agents that operate on our resource-constrained edge devices.
Integrate deep domain knowledge, including real-time log analysis, computer vision, and interaction with open-source system tools.
Security & Optimization:
Define and implement the complete security and verification framework for our edge models. This includes MCP/A2A-like secure protocols, MCP authentication, entity verification (e.g., model signing), and model injection prevention.
Serve as the primary technical bridge to our silicon teams. Collaborate with RTL designers to influence future NPU and FPGA architecture from an ML software perspective.
Lead R&D on model optimization for our specific AI inference engine, applying both graph-level (e.g., operator fusion) and OP-level (e.g., custom ops) techniques.