Axiado Corporation is seeking a Senior IC Packaging Engineer to provide technical leadership and architectural ownership of advanced IC and System-in-package(SiP) in a fast-growing startup environment. This role is designed for a senior technologist who combines deep hands-on expertise with system-level thinking, and who thrives in high-ambiguity, high-impact settings.
You will define and drive high-performance, low-power packaging architectures spanning 2D and RDL based fan-out (2.5D), chiplet-based designs, and heterogeneous integration, leading efforts from early technology path finding through production ramp. You will work closely with foundries, OSATs, substrate suppliers, and internal cross-functional teams to shape both product execution and long-term packaging strategy.
Key Responsibilities
- Serve as technical authority for IC and SiP packaging across multiple products and programs.
- Own package architecture and technology roadmap, aligned with product, cost, and scalability goals.
- Lead chiplet-based packaging strategies, including UCIe, silicon interposers, and advanced RDL.
- Perform and guide hands-on package design and physical layout, including critical structures for High-speed SerDes/PHY (PCIe, CXL), LPDDR5, UCIe, and Other multi-gigabit interfaces.
- Define substrate stack-ups, materials, bump/RDL architectures, and DFM guidelines for advanced nodes.
- Drive SI/PI, thermal, mechanical, and reliability trade-offs at the system and package levels.
- Lead external engagement with OSATs, foundries, and key suppliers for technology development and manufacturing readiness.
- Influence product roadmap, risk management, and investment decisions through technical insight.
- Establish scalable design methodologies, best practices, and reusable packaging flows.