As a Physical Design Engineer, you will be responsible for planning, designing, and validating power delivery networks (PDN) for System-on-Chip (SoC) and custom IPs. You will leverage Fusion Compiler for PDN implementation and collaborate closely with IP partition owners, IR and reliability owners, and dedicated IR/EM/power integrity engineers to understand power requirements and ensure robust PDN solutions.
Your responsibilities will include but are not limited to:
• Planning and designing PDN for SoCs and custom IPs using Fusion Compiler.
• Performing layout verification of the PDN network and clearing all DRCs (Design Rule Checks).
• Collaborating with IP partition owners, IR/reliability owners, and dedicated IR/EM/power integrity engineers to gather power requirements and implement them in PDN design.
• Ensuring PDN meets performance, reliability, and area goals.
• Applying best-known methods to create high-quality PDN layouts efficiently.
The ideal candidate should exhibit the following behavioral traits:
• Strong problem-solving and teamwork skills.
• Effective communication and collaboration across teams.
• Attention to detail and adaptability.
• Ability to work independently and proactively address design challenges.
Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications:
• BTech in Electrical or Electronics Engineering with 3+ years of relevant experience OR MTech in VLSI or related field with 2+ years of relevant experience.
• Experience with Fusion Compiler.
• Technical skills required for PD engineers.
Preferred Qualifications:
• Scripting experience with TCL for automation.
• Relevant expertise in PDN design and implementation.
• Experience in layout design or LV (Layout Verification) cleanup using Synopsys Fusion Compiler (FC) or ICC.
Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.*
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