Job Details:

Job Description:

Intel put Silicon in Silicon Valley. No one else is obsessed with engineering and has a brighter future. Every day, we create world changing technology that enriches the lives of every person on earth. So, if you have a big idea, let's do something wonderful together. Join us, because at Intel, we are building a better tomorrow.

The Role and Impact:
Join Intel as a CPU Logic Design Engineer in Chandler, AZ or Austin, TX and play a pivotal role in advancing cutting-edge semiconductor technology. You will be at the forefront of designing and developing CPU logic, ensuring power, performance, and area optimization to meet Intel's world-class standards. As part of our innovative engineering team, your contributions will directly impact the success of Intel's CPU designs and their integration into system-on-chip (SoC) solutions. This is an exciting opportunity to shape the architecture and microarchitecture of CPUs, influencing the development of industry-leading processors that power the future of computing.

Key Responsibilities:

• Develop logic design, register transfer level (RTL) coding, and simulation for CPUs, creating functional units, cell libraries, and CPU IP blocks for integration into full-chip designs.
• Define and contribute to the architecture and microarchitecture features of the CPUs being designed.
• Apply strategies, tools, and methods to write RTL code, optimizing logic for power, performance, area, and timing goals, as well as ensuring design integrity for physical implementation.
• Collaborate on verification planning and implementation to validate design features, identifying and resolving RTL test failures to ensure correctness.
• Document microarchitectural specifications (MAS) for CPU features and provide necessary support to SoC customers to ensure high-quality integration of CPU blocks.
• Debug and resolve complex cross-domain issues that span RTL, tools, and software domains.
• Supports SoC customers to ensure high quality integration of the CPU block.

Qualifications:

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your degree, research and or relevant previous job and or internship experiences.

Minimum Qualifications:
Bachelors in Computer Engineering or Electrical Engineering Computer Architecture with 4+ years of experience listed below -or- Masters degree with 3+ years of experience listed below.

• 4+ years experience in hardware description languages such as Verilog and System Verilog and familiarity with tools like VCS or Questasim.
• 3+ years experience in programming experience in Perl, Python, or C/C++, with advanced debugging skills in complex environments and RTL Verilog coding, hardware modeling issues, and logic debug environments.
• 3+ years experience in designing coherent systems with advanced queues/pipelines, external bus interfaces, snoop filters, and L2 cache featuring ECC, MCA, and repair mechanisms.
• 3+ years experience in scripting in an interpreted language (e.g. TCL, Perl, Python, Ruby) and/or using AI to generate/edit scripts.

Preferred Qualifications:

• Ability to effectively communicate complex technical concepts to cross-disciplinary teams and stakeholders.
• Proven problem-solving skills and experience working in collaborative, fast-paced environments.
• Experience in modern, energy-efficient/low-power logic design techniques, including those specifically applicable to high frequency timing convergence.
• Good communication skills

          

Job Type:

Experienced Hire

Shift:

Shift 1 (United States of America)

Primary Location:

US, Arizona, Phoenix

Additional Locations:

US, Texas, Austin

Business group:

Silicon and Platform Engineering Group (SPE): Deliver breakthrough silicon and platform solutions that deliver industry-leading products today while also defining the next generation of computing experiences.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $122,440.00-232,190.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

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ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.