We are seeking a Technologist, Mask Design Engineering specializing in Memory Technology to join our innovative team in Seoul, South Korea.
In this senior-level role, you will lead the mask layout design for peripheral circuit and working across global teams to enable successful tape‑outs.
This role is intended for recognized technical leaders who combine deep layout expertise (STD/Block layout, signal/power planning, Floor Planning and full chip integration), strong verification skillset, and thinking, and who maintain both layout quality and layout schedule across projects. Furthermore, you are expected to take the lead in enhancing the overall capabilities of the team and improving layout design quality through mentorship and technical guidance provided to junior engineers.