Principal Engineer, ASIC Development Engineering (Physical verification Engineer)

JOB Description :
 

• Take the leadership role of executing and signing off physical verification for block and full chip.
• Strong fundamentals in physical design verification using Calibre tool.
• Strong experience in multi voltage domain and design experience with multi-million instances.
• Work with the PD team to clean up all DRC/LVS/ESD/ERC/ANT violations and sign off PV for tapeouts
• Experience of working in lower tech nodes (TSMC5nm and below)
• Familiarity of PnR flows and tools such as Cadence Innovus/FC is must.
• Knowledge and hands on virtuoso experience is plus.
• Experience in power gating digital designs is a plus.
• Excellent verbal and written communication skills are required.
• Perform block and full-chip physical verification and work with the physical design team to close design issues
• Experience level : Minimum 9+ years