Sandisk鈥檚 ASIC team builds state-of-the-art memory controllers that power world-class NAND Flash products used globally at massive scale. Design Enablement team enables the Technology, Methodology and Flows to the Mixed Signal IP team to deliver best in class products. As the MSIP CAD/Methodology Engineer, you will play a pivotal role in developing, and delivering robust MSIP Design methodologies on cutting-edge technology nodes, enabling best-in-class quality and productivity.
This role is ideal for a seasoned MSIP methodology leader who enjoys solving complex cross-domain problems, working closely with foundries, and driving innovation across flows, tools, and teams.
Key Responsibilities
Mixed-signal IP CAD and methodology development, covering schematic, layout, verification, and signoff flows.
Architect and maintain end-to-end custom design methodologies, from transistor-level design through signoff-ready layouts.
Drive layout quality standards, including matching, symmetry, parasitic control, reliability, and manufacturability.
Define and enforce physical verification methodologies, including:
DRC
LVS
PERC
Reliability and signoff checks
Own and evolve signoff methodologies for mixed-signal IPs, including EM/IR analysis and reliability verification.
Work closely with custom circuit designers and layout teams to identify recurring issues and introduce automation, checks, and best practices.
Collaborate with foundry counterparts to understand process-specific constraints, reliability requirements, and rule interpretations.
Develop correct-by-construction and shift-left flows to catch issues early and reduce iteration cycles.
Drive tool qualification, flow robustness, and productivity improvements across multiple IP programs.
Mentor engineers and foster a culture of quality, rigor, and innovation within the CAD/methodology team.