Principal AI Interconnect Architect

An AI Interconnect Architect defines and engineers high-speed networking and communication systems for AI Inference infrastructure which include servers, racks, and chips with a focus on bandwidth, power efficiency, scalability, and optimized transport protocols. Design solutions should take into account interconnect technologies such as PCIe, CXL, co-packaged optics, UALink, Ultra Ethernet, and be able to specify innovative scale-out architectures for optimizing power, cost, and performance. 

Essential Duties and Responsibilities: 

• System Architecture & Design: Develop architectures for chip-to-chip interconnects and switched fabrics tailored for AI/ML scale-out. 
• Performance Optimization: Analyze trade-offs in bandwidth, latency, power, area, and reliability. 
• Technology development and standards: Participate in industry standard bodies and contribute/influence/shape the direction of industry specifications.
• Cross-functional Collaboration: Work with SoC, package design, and software teams to ensure seamless integration