Sandisk’s ASIC team builds state-of-the-art memory controllers that power world-class NAND Flash products used globally at massive scale. Design Enablement team enables the Technology, Methodology and Flows to the Physical Design team to deliver best in class products. As the PD Methodology / CAD Engineer, you will play a pivotal role in defining, architecting, and delivering robust RTL-to-GDS physical design methodologies on cutting-edge technology nodes, enabling best-in-class PPA, quality, and productivity.
This role is ideal for a seasoned PD methodology leader who enjoys solving complex cross-domain problems, working closely with foundries, and driving innovation across flows, tools, and teams.
Key Responsibilities
Drive continuous improvement in PPA (Power, Performance, Area) and turnaround time through flow optimization, automation, and best practices.
Work closely with foundry partners to understand node-specific challenges (design rules, variability, EM/IR, signoff requirements) and develop correct-by-construction solutions.
Collaborate with IP teams, RTL design, DFT, and signoff teams to address cross-domain optimization challenges and enable smooth design convergence.
Develop “shift-left” and “push-up” methodologies to detect and resolve issues early in the design cycle, improving predictability and schedules.
Deliver high-quality, signoff-clean flows with strong emphasis on reliability, yield, and manufacturability.
Leverage AI/ML techniques to improve quality, debug efficiency, predict design issues, and enhance overall productivity.
Foster a culture of technical excellence and innovation, encouraging the team to develop novel solutions for next-generation challenges.