We are seeking an experienced Senior IP Verification Engineer to join our design verification team. The ideal candidate will be responsible for developing and executing comprehensive verification strategies for complex digital IP blocks, ensuring functional correctness and performance compliance before tape-out.
ESSENTIAL DUTIES AND RESPONSIBILITIES:
- Develop comprehensive verification plans and testbenches using UVM methodology
- Create reusable verification components (UVCs) including agents, monitors, drivers, and scoreboards
- Design constrained-random stimulus and coverage-driven verification strategies
- Debug RTL issues, perform root cause analysis, and work closely with design teams
- Develop and maintain regression test suites and coverage metrics
- Mentor junior engineers on UVM best practices and verification methodologies
- Review and improve verification infrastructure and coding standards
- Contribute to IP-level and SoC-level integration verification