ESSENTIAL DUTIES AND RESPONSIBILITIES:
- Drive NAND development from pre-silicon (circuit simulation for stress/screen test method), 1st silicon to qualification from DPPM (Defective part per million) perspective.
- Own and achieve DPPM (Defective part per million) targets on SD NAND Technology in line with technology & product roadmaps.
- Develop and define test strategy and test flow for SD NAND Technology on DOEs from dedicated Memory Health R&D line.
- Develop and define screen/stress strategy, algorithm, method, and spec for miscellaneous NAND silicon.
- Closely co-work with Fab technology development team to drive process improvement and countermeasure for failures revealed from MH R&D line.
- Collaborate with Flash BU (System/FW team) to develop error handling algorithms in system & firmware level.
- Work with PE/TE to come up with detail plans and drive for implementation on test flow, stress & screen developed from MH.
- Performing deep electrical failure analysis during new technology development and qualification phase. Define the action plans after communication with stockholders (Device engineer, Design engineers, Fab product engineer, etc.)
- Monitor memory health level and DPPM pareto for miscellaneous product lines. Work with FAB/device to improve and fine tune the fab process for DPPM reduction.