This role is the most senior technical individual contributor in memory design. Owns end-to-end product architecture from concept through silicon qualification, arbitrates the power/performance/area trade-offs that set competitiveness, and is the final technical authority across design, process and product engineering.
- Define the memory subsystem architecture (array, periphery, I/O, redundancy, test, reliability) and turn product requirements into a design spec
- Drive floorplan and physical architecture: array efficiency, periphery partitioning, power delivery, die-level signal integrity
- Own the multi-generation roadmap: node migration, density and performance scaling
- Decide cross-functional trade-offs across process integration, circuits, DFT, packaging and controller/firmware interfaces
- Own design methodology and EDA/CAD strategy: tools, flows, vendors, licenses
- Mentor senior and principal engineers through architecture and design reviews
- Represent the architecture to executives, customers, foundry partners and standards bodies