Northrop Grumman Space Systems is looking for aStaffFPGADigitalEngineertosupport the Electro-Optics(EO)Groupwithinthe Launch Vehiclesbusiness unitinChandler, Arizona.
As a Staff FPGA design engineer, you will apply advanced understanding and wide application of FPGA engineering principles, including mastery of methods and tools available for solving complex technical challenges. You will work closely with senior staff, junior staff,andcross-disciplinary teams (hardware, algorithms, and software)to provide technical solutions to a wide range of complex problems.The ideal candidate excels in fast-paced, collaborative environments and is comfortable managing multiple diverse assignments.
Responsibilities:
Lead resolution of design and integration challenges, drawing on advanced technical knowledge and wide application across disciplines.
Develop and execute high-level test benches to verify FPGA designs for functional correctness and timing requirements, managing configuration of multiple FPGA bitstream builds.
Generate, verify, and integrate IO and image processing HDL modules, including functions definitions, HDL coding, module-level simulation, and integration with device architecture.
Ensure compliance with internal design standards throughout the development lifecycle and mentorless experiencedengineers.
Prepare, present, and maintain comprehensive design documentation including schematics, simulation results, and verification reports.
Stay abreast of evolving FPGA technologies, tools, and industry methodologies, demonstratingmastery in methods and tools available for addressing technical issues.
BasicQualifications:
Bachelor’s degree inElectrical Engineering, Computer Engineering,or related discipline from an accredited university and12years of relevant experience; or a Master’s degree and10years of experience; or a PhD and8yearsof experience.
Ability to obtain a U.S. Government Department of Defense (DoD) Secret security clearance at the time of application.
Advanced background in FPGA/SoC design,with mastery in complex firmware developmentusing VHDL (preferred) or Verilog.
Extensiveexperience with AMDXilinxFPGAs and SoCs, with proficiency in managingdesign constraints (timing, power, I/O) and performing static timing analysis to achieve critical performance targets.
Advanced proficiencyin development, verification, and debugging ofMOSA interfaces/buses (Ethernet, PCIe, AXI4, UART, and SDLC)
Masterywith simulation tools (Questa/ModelSim) and hardware debugging tools (logic analyzers, oscilloscopes).
Strong experience creating and executing verification plans using simulation, analysis, and hardwarebenchtesting.
Deep knowledgeofOpen Source VHDL Verification Methodology (OSVVM) or Universal Verification Methodology (UVM). OSVVM preferred
Preferred Qualifications:
MS or PhD inElectrical Engineering, Computer Engineering, or related discipline.
ActiveU.S. Government DoD Secret security clearance at the time of application.
Experience with missile systems, seeker systems, or other high reliability, environmentally challenging electro optical applications.
Prior experience withDoD missile defense programs and associated standards.
Direct experience with AMD XilinxVersal Gen 2 or Gen 1
Masterywith bothVivadoIDE andVitis Unified IDE.
Advanced experience designing, integrating, and verifying DDR memory interfaces (e.g., DDR3/DDR4/DDR5)withfabric-based controllers in FPGA designs.
Deep understanding of embedded C/C++ programming for integration with processors/SoCs.
Knowledge of high-speed PCB design and signal integrity.
Strong experience with OSVVMor UVM.
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