[EMN] Senior IP Design Verification Engineer (5-10 YoE)

About the Role

As a Senior IP Design Verification Engineer, you will play a key role in ensuring the functional correctness, interoperability, and quality of advanced Silicon IPs for next-generation System-on-Chip (SoC) platforms. You will own pre-silicon verification from planning through sign-off, developing robust UVM/SystemVerilog verification environments and driving complex debugging across IP and system boundaries. You will work with advanced interfaces and protocols, including UCIe and AXI, while contributing to the technical excellence of Bosch’s Automotive Chiplet Systems (ACS) project.

Learn more about Bosch’s Automotive Chiplet technology: https://www.bosch-semiconductors.com/stories-and-events/chiplet-revolution/

Responsibilities

• Own and execute Silicon IP based pre-silicon verifications (verify e.g. UCIe Interoperability) from planning through verification sign-off.
• Develop, enhance, and maintain verification environments, testbenches, test cases, checkers, and coverage models.
• Run simulations and regressions, analyze failures, debug issues, and drive root-cause resolution with IP, integration, and system teams.
• Track verification progress, report status clearly, highlight risks early, and propose mitigation actions.
• Review verification results, ensure process compliance, and contribute to technical reviews and design-verification discussions.
• Guide junior engineers on verification methodology, debugging approach, and efficient execution of assigned tasks.