Our vision is to transform how the world uses information to enrich life for all.
Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing.
As a SparesEngineeringEngineer,you will:
Be a key driver in executing and managing programs within the Spare Engineering function — spanning both Spares Initiatives for Cost, Productivity,Quality and TestWafer management. You will work in a fast-paced semiconductor environment, applying your technicalexpertiseand program management skills tooptimizeefficiency, control test waferutilization, align with demand, and deliver measurable results — all while collaborating across global teams and Sites
Responsibilities
Spares Engineering
Lead and execute sparesengineering programsto drive operationaland costefficiency
Analyze metrics and demand trends toidentifyand act on improvement opportunities
Drive programs in a structured and systematic manner, ensuring milestones, timelines, and deliverables are consistently met
Identifyprocess gaps and bottlenecks within sparesengineering and implement effective corrective actions
Develop and present program status updates, reports, and recommendations to key stakeholders
Support technical aspects for Spares Relatedissuesanddrivefor consistent improvement throughcollaboration with Suppliers
Be acategory leader leading global strategyfor Spares Lifetime, CCRR, Alternate Sourceand consumption reduction activities
Test Wafers
Coordinate with process and equipment engineering teams tooptimizetest wafer usage and minimize waste as well asfabadditionalspace creation.
Establish andmaintaintest wafer planning processes aligned with engineering demand and capacity
Monitor test waferutilizationtrends and provide data-driven recommendations to reducecostsand improve efficiency
Ensure proper documentation, traceability, and compliance for all test wafer transactions and usage records
Shared / Common
Collaborate cross-functionally with engineering, operations, supply chain, and leadership teams
Travel to multiple sites orSupplierlocations asrequiredto support program execution
Maintainaccuratedocumentation and ensure compliance with engineering standards and best practices
Cross‑Functional&Cross‑SiteCoordination
Enablecollaboration across stakeholders including FE central planning functions,fabplanning teams, SMAI, OCT and other central teams.
Act as a central integration point to ensure alignment across regions, functions
Support recurring global forums andprogramsspecific reviews to ensure consistent execution and escalation of issues.
External Benchmarking and Analysis
Lead analysis and benchmarking efforts with competitors fromSpares and Test Wafer front
Identifyopportunities for improvement
AI Responsibilities
Requirements:
Bachelor's degree or higher in Engineering (Electrical, Mechanical, Industrial,Materials, or related discipline) from an accredited university, OR equivalent engineering training/certification
~6years of experience in the semiconductor industry
Demonstrated experience in engineering program management or productivity-related initiatives
Strong understanding of productivity concepts,demand planning principles
Familiarity with semiconductor wafer processes, test wafer usage protocols, or related engineering operations
Preferred Qualifications
Experience in spare parts management, equipment engineering, or semiconductor manufacturing environments
Familiarity with structured methodologies such as Lean, Six Sigma, or PDCA
Proficiencyin data analysis tools such as Excel, Power BI, or equivalent platforms
Experience presenting to and influencing senior stakeholders
Hands-on experience with test wafermanagement,fabcost control,maxoutprograms
Understanding of wafer process flows and how test wafers are consumed at each engineering stage
Additional Requirements