Position Overview:
We are seeking an exceptionally skilled and strategic Technologist for our Static Timing Analysis (STA) function. The successful candidate will serve as a technical leader and subject matter expert, guiding a team of talented engineers and driving innovation in timing closure methodologies for our most complex semiconductor designs. This role demands deep expertise in STA, proven leadership in cross-functional collaboration, architectural thinking, and the ability to influence technical direction across multiple projects and organizations.
Key Responsibilities:
- Lead a team of talented STA engineers , observe complete ownership of ASIC timing signoff across , fostering technical growth, and building a high-performing organization capable of delivering excellence in timing closure for complex semiconductor designs.
- Architect and define organization-wide STA methodology and standards, establishing best practices, signoff frameworks, and quality metrics that enable consistent, scalable timing closure across all ASIC projects and process nodes.
- Work with IP & Design team for Timing constraints Development & Review activities.
- Develop and implement advanced STA methodologies and strategies to meet the timing closure requirements of complex IC designs.
- Collaborate with cross-functional teams, including design, verification, physical design, and DFT, to ensure seamless integration and optimal timing performance.
- Conduct thorough timing analysis, identify critical paths, and develop strategies to mitigate timing violations and improve overall design performance.
- Stay abreast of industry trends and emerging technologies in STA and related fields, and incorporate best practices into the team’s workflow.
- Prepare and present detailed timing reports and technical documentation to stakeholders
- Foster a culture of innovation, collaboration, and continuous improvement within the STA team.