This role primarily supports Foundry PDK teams and Design Service teams by enabling EM/IR and thermal signoff technologies through robust techfile development and reference flow creation.
• Support foundry PDK teams in development and validation of EM/IR and Thermal techfiles for Voltus and Celsius.
• Define and validate power integrity, EM, and thermal modeling assumptions aligned with foundry signoff requirements.
• Collaborate with PDK, extraction, and signoff teams to ensure tool readiness for advanced-node and 3DIC processes.
• Develop and maintain design reference flows for EM/IR and thermal signoff used by design service teams.
• Support hierarchical and full-chip signoff flows from early design stages to tape-out.
• Provide flow debugging and convergence support for large SoC and multi-die designs.
• Static/Dynamic IR drop and EM signoff using Voltus.
• Electro-thermal co-analysis using Voltus and Celsius.
• Advanced-node, chiplet, and 3DIC thermal analysis.
• Strong understanding of EM/IR and thermal fundamentals.
• Experience with UNIX/Linux environments and Tcl/Python scripting.
• Familiarity with digital backend and signoff flows.
cadence