SSG Internships Summer 2025
The Cadence Silicon Solutions Group (SSG) develops industry-leading Digital IP (Intellectual Property), from RISC-V processor cores to DSPs to Memory Controllers and IO solutions. Our configurable and extensible IP solutions are poised to meet the demands of next-generation applications such as intelligent IoT Devices and ML/AI edge inference. Essentially, all leading semiconductor providers can be counted as Cadence customers.
The Cadence SSG Team is hiring students to join our R&D teams in San Jose or Austin. This is an amazing opportunity to work at a world leader in computational software, semiconductor design IP, and system verification hardware. Our customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to complete systems for the most dynamic market applications, including hyperscale computing, 5G communications, automotive, mobile, aerospace, consumer, industrial, and healthcare.
We aim to make you an integral part of the team by providing training, mentorship, and encouragement of your creative talents. Our goal is to equip students with practical work experience. We understand that it is best to learn by doing. We will provide tasks that enable you to learn while making meaningful technical contributions.
Come be part of this great SSG Team where your contributions can make a visible impact. Your work will be integral to our success and the advancement of our industry.
Description: Signal Integrity Validation Internship
In this position, you will be working with a team of Signal Integrity Engineers. Your scope of responsibilities will include but are not limited to:
Performing modeling and simulation of high-speed interface interconnects/channel. Working in lab to perform measurement, and correlating measurements to simulations. Working with silicon designers, platform designers, package designers, electrical validation teams, etc. to support interconnect and interface performance requirements. Contributing to package and platform design guideline development. Reviewing and evaluating package and board design and providing review feedback; Electrical modeling and simulation of high-speed IO interconnects, such as DDR. Development of package and platform design guidelines. Definition and evaluation of circuit design features required to support interconnect performance requirements. Creation of signal measurement test plans and review of measurement results. Correlation of measurements to simulations, and modification of models as required. Support signal integrity tool and methodology development.
Position Requirements:
Minimum Qualifications
The hourly range for California is $31.63 to $58.75 per hour. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Please note that the hourly range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.
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