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Broadcom offers an excellent opportunity to contribute to a team environment and to grow personal career path. You will be working with internal and external customers to develop state of the art IC solutions utilizing Broadcom's leading edge CMOS cell-based ASIC technologies. You will have responsibility for ASIC designs through all of the key development and implementation phases including RTL analysis, synthesis, design optimization, timing verification, simulation, test insertion, physical design, vector generation, and post-prototype test support. Candidates will have opportunity to work on the latest 5nm/3nm designs
Responsibilities:
1.Participate in chip level DFT architecture definition.
2.Implement basic DFT schemes, including scan, boundary scan, MBIST, Logic BIST and SSN
3.Verify all DFT logics and test patterns with simulation
4.Test modes static timing analysis
5.Participate in ATE bring-up and debug the DFT patterns on ATE.
Requirements/Qualifications:
1.Either Bachelor or Master degree, 5+ years related experience required.
2.Good understanding of the General DFT methodology such as BIST, SCAN, JTAG and ATPG
3.Be familiar with basic Mentor/ Synopsys DFT flow and tools
4.Experience in developing constraints for synthesis/STA
5.Multi-mode, multi-corner STA experience, Understanding Sign-Off Checks
Education/Certifications
Preferred Degree: MS Preferred Major: Microelectronics or related discipline
Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.
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