Job Details:

Job Description:

About Altera

At Altera™, our independence as the world’s largest pure-play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise. With more than four decades of industry-leading FPGA expertise, our singular mission is to deliver the programmable technologies that help customers differentiate, innovate, and scale across rapidly evolving markets like AI, cloud, networking, and edge. As an independent company, we move faster, invest deeper, and partner more closely—empowering our teams to drive breakthrough innovation and shape the future of the FPGA industry.

About the Role

Join Altera as an FPGA Silicon Design Engineer focused on RTL design. In this role, you will be responsible for developing high-quality logic designs and RTL implementations for next-generation FPGA products. You will collaborate cross-functionally with architecture, verification, and physical design teams to deliver robust, high-performance silicon solutions. This position plays a critical role in enabling scalable, power-efficient FPGA architectures used across a wide range of applications.

Key Responsibilities

• Develop logic design, register transfer level (RTL) coding, and simulation for FPGA components including cell libraries, functional units, IP blocks, and subsystems.

• Participate in defining architecture and microarchitecture features of assigned design blocks.

• Create prototypes, simulate models, and define system requirements for new designs.

• Prepare and design logic diagrams and RTL code to implement system design and test specifications.

• Deliver software models to support device-level bring-up, including functionality, timing, and power characteristics.

• Apply RTL implementation techniques to meet power, performance, and area (PPA) goals in partnership with physical design teams.

• Review verification plans and ensure proper implementation to validate design features.

• Debug failing RTL tests, identify root causes, and implement corrective actions to ensure design correctness.

Salary Range

Qualifications:

Minimum Qualifications

• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, Physics, Math, or related field and 8+ years of industry experience in FPGA or ASIC design.

• 8+ years of experience in RTL design and coding using SystemVerilog and/or Verilog for complex digital systems.

• 8+ years of experience with programming/scripting languages such as Python for design automation, modeling, or verification support.

• 8+ years of experience in hardware design concepts including logic design, finite state machines, control units, processor subsystems, and network-on-chip (NoC) architectures.

• 8+ years of experience using industry-standard front-end design tools and flows, including synthesis, static timing analysis (STA), linting (e.g., SpyGlass), and power domain methodologies.

• 8+ years of experience collaborating with cross-functional teams (verification, physical design) to achieve power, performance, and area (PPA) targets.

Preferred Qualifications

• Knowledge of Network-on-Chip (NoC) architectures and control processors.

• Experience contributing to silicon bring-up or post-silicon validation.

• Experience or knowledge in FPGA configuration controllers

Job Type:

Regular

Shift:

Shift 1 (United States of America)

Primary Location:

San Jose, California, United States

Additional Locations:

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.