Job Details:

Job Description:

Role Overview

Seeking an experienced Signal Integrity & Power Integrity (SI/PI) Engineer with 7+ years of experience; responsible for the design, verification, and optimization of high‑speed interconnects across IC package and board‑level architectures.

This role includes delivers signal integrity solutions for large, complex high-speed platforms, boards, and packages. Develops a viable space for all interconnects including 2D and 3D models extracts of electrical structures for the entire die-to-die interconnect. Defines signal integrity rules, reviews implementation, documents characterization and measurement reports, and improves and optimizes design margins. Applies knowledge of signal integrity design and tradeoffs to perform simulations of interconnect and guide package and platform physical implementation, and designs and characterizes test structures to correlate simulations and measurements for interconnects using intricate high-speed equipment and debugs challenges. You will collaborate closely with leading SI/PI experts, silicon architects, package engineers, and board design teams throughout the product pathfinding and development phases. Leveraging advanced electrical modeling and simulation, the candidate should drive the optimization of FPGA electrical performance on validation boards (mUDV, mUCV and Dev Kit), ensuring our products achieve industry‑leading signal quality, robust power delivery, and best‑in‑class performance while maintaining cost‑effective design trade‑offs. Exposure to silicon validation and characterization platforms will be good to have.

Key Responsibilities

• Lead the signal & power integrity simulations for the end‑to‑end design and development of validation hardware platforms and development kits, ensuring our products achieve industry‑leading signal quality, robust power delivery, and best‑in‑class performance while maintaining cost‑effective design trade‑offs.
• Expertise in complex processor-, FPGA-, and ASIC‑based systems, ensuring alignment with platform performance, power, and cost objectives.
• Simulate and review board level circuit designs, trade‑off analyses to ensure robust and scalable hardware solutions.
• Review and sign off mUDV, mUCV and Dev Kit board tape outs, including high‑speed routing constraints, signal/power integrity simulations results and stack‑up considerations.

• Responsible to drive the Signal and Power integrity simulations and sign-off on PCB pre-and-post layout, Power Distribution Network (PDN), and design reviews from on board critical signals and power integrities through board tape‑out.

• Resolve complex system-level signal and power integrities issues across electrical, mechanical, thermal, and manufacturing domains.

• Work closely with cross-functional teams including platform architects, board design engineers, validation, and customer engineering.
• Integrate feedback to continuously refine design methodologies and enhance platform robustness.

Qualifications:

• Bachelor’s degree in electrical engineering, Computer Engineering, or a related discipline, with strong academic background in electromagnetics, circuit analysis, and signal processing.
• Minimum of 7+ years of hands‑on experience in Signal Integrity and Power Integrity engineering within silicon, package, and board‑level design environments.
• Deep expertise in SI/PI principles, high‑speed digital signaling, and power delivery network behavior. Proficiency with industry‑standard simulation and modeling tools such as ANSYS HFSS, Synopsys HSPICE, Cadence Sigrity, Keysight ADS, and equivalent platforms.
• Strong analytical capability to evaluate, interpret, and correlate simulation results with design and measurement data.
• Excellent problem‑solving skills with the ability to diagnose and resolve complex SI/PI issues across multi‑domain design spaces.
• Hands‑on experience with PCB design and layout tools such as Mentor Graphics or Cadence Allegro. Scripting and automation skills using Python, MATLAB, or similar languages are highly desirable.

Job Type:

Regular

Shift:

Shift 1 (Malaysia)

Primary Location:

Penang 15, Penang, Malaysia

Additional Locations:

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.