Altera offers a large selection of intellectual property IP cores optimized for Altera FPGA devices, all of which are developed for highest performance, lowest cost, ease of use and fastest time-to-market.
The FPGA IP System & Solution Engineering group is responsible for High Speed Protocol IP development, which includes participating in high-level product specifications, logic/RTL design and implementation, RTL verification, IP FPGA emulation prototyping and hardware validation.
In the role of Senior IP Design Engineer specializing in FPGA Soft IP RTL development, you will be responsible for designing, developing, and verifying wireless IP cores for FPGA platforms, while working closely with system architects, verification engineers, and software teams to deliver reliable and high-performance wireless solutions.
Bachelor's degree in Electrical, Electronics, Computer Engineering or equivalent.
Proficiency in Verilog/System Verilog, RTL design coding.
Experience in FPGA, custom IC or ASIC design, demonstrated excellence in any of the product development areas from architecture, design, validation to product.
Familiarity with simulation and verification tools (Synopsy VCS, Questa, Modelsim, etc.).
Knowledge of high-speed serial interfaces such as Ethernet, CPRI, and eCPRI, along with familiarity with O-RAN architectures, is a strong plus.
Understanding of timing closure, clock domain crossing, and FPGA constraints.
Familiarity with Perl, TCL, Python and shell scripts is a plus.
Strong written and verbal communication skills to work with cross‑functional team.
Demonstrates fundamental values such as accountability, integrity and a winning mindset.
Strong analytical and problem-solving skills, with a proactive mindset that promotes innovation and teamwork.
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