Cadence is searching for a Software Engineer to work on delay calculation and signal integrity (SI) analysis in Static Timing Analysis tool. Responsible for implementing and extending existing capabilities for circuit and interconnect delay and signal integrity analysis of large scale circuits, investigating techniques to improve correlation of delay/SI analysis to SPICE, and modeling of nanometer circuit effects in delay/SI analysis.
Position Requirements:
The candidate should have MS/PhD in EE/CS or related discipline, strong programming skills in C++, and deep familiarity with object-oriented programming methods. Prior knowledge and experience with multi-threaded programming, numerical analysis techniques, and delay calculation methods for nanometer circuits preferred.
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