Altera, a leader in programmable solutions from cloud to edge, delivers cutting-edge FPGA, CPLD, and IP technologies. We are driving innovation in high-speed connectivity, AI acceleration, and next-generation data infrastructure. Our mission is to empower engineers to design and deploy advanced systems with unmatched flexibility and performance.
We are seeking a talented Logic Design Engineer to develop and optimize mixed-signal and high-speed IPs for integration into full-chip designs.
Key Responsibilities:
1-Participate in design development tasks throughout the IP development flow.
2-Develops the logic design, register transfer level (RTL) coding, and simulation for an IP.
3-Develops the logic design, register transfer level (RTL) coding, and simulation for an IP required to generate cell libraries, functional units, IP blocks, and subsystems for integration in full chip designs.
4-Applies various strategies, tools, and methods to write RTL and optimize the logic to quality the design to meet the IP release requirement.
5-Involve in design example creation, simulation example creation, IP integration and release process.
6-Involve in IP design example brings up on hardware, hardware verification and failure debugging.
3+ Years experience bachelor's or master's degree in electrical engineering, Computer Engineering, or a related field.
Experience in System Verilog, VCS/Synopsys simulators, Lint and Synthesis
Experience in programming with C/C++/Perl/Python/TCL/Unix Shell script
Experience in FPGA design and programming is a plus.
Experience in RTL validation is a plus.
Ability to work with different teams, good communication and problem-solving skills.
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