Principal Engineer, Package Co-Design

We are seeking a highly experienced Principal Engineer, Package Co-Design Leader with strong experience in Packaging and Die-Package Co-Design. This role requires deep expertise in different packaging technologies, die/package co-design interactions, signal/power integrity, thermal, and mechanical considerations. 

Principal Engineer, Package Co-Design

About GlobalFoundries:

GlobalFoundries is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world’s most inspired technology companies. With a global manufacturing footprint spanning three continents, GlobalFoundries makes possible the technologies and systems that transform industries and give customers the power to shape their markets. For more information, visit www.gf.com.

Introduction:

We are seeking a highly experienced Principal Engineer, Package Co-Design Leader with strong experience in Packaging and Die-Package Co-Design. This role requires deep expertise in different packaging technologies, die/package co-design interactions, signal/power integrity, thermal, and mechanical considerations. 

 

Key Responsibilities:

• Lead die-package co-design strategy for custom silicon products developed by MIPS covering industrial, automotive and other end-equipment. Drive the overall packaging engagement on these products.

• Define package architecture, selection in alignment with silicon floorplan, bump layout, and IO planning. Drive early feasibility studies, trade-off analysis across performance, cost, signal integrity, thermal and manufacturability. Drive as technical liaison and direct the overall package solution and architecture.

• Drive Package co-design design and related Engineering work. Work on interface placement, IO ring development and overall die floorplan to optimize package routing, escape routing and bump/pad alignment. Work with SoC design team on power grid integration and design for signal and power integrity

• Cross-collaboration and system level leadership working closely with different disciplines such as SoC Design, Board/System level design, and customers to develop compelling and differentiated solutions. Strong understanding of package level issues, performance, cost trade offs, reliability considerations and proven track record in driving technology, vendor engagements

• Driving system level analysis performing and guiding signal integrity (SI), power integrity (PI), thermal analysis, and mechanical analysis simulations. Drive a co-design methodology and approach across die, package, board level designs.

• Validation and Characterization skills on post-silicon. Ability to define validation and characterization requirements for new productions. Understanding spec compliance requirement needs and drive validation teams. Define architecture to meet Design For Test (DFT) / Design for Manufacturing (DFM) requirements. Support silicon-package interaction issues during bring-up and validation 

• Mentorship and leadership in providing technical guidance and mentorship to other junior engineers working in the team. Lead and Manage the team in setting the team direction, align with business and product priorities and drive on-time deliverables. Providing technical guidance and technical SME across teams on topics related to analog, mixed signal

• Customer and vendor engagement leadership to drive technical alignment, discussions and execution. Drive customer discussions and align both internal product and technology roadmaps. Drive direct support of customers on topics related to packaging

• Stay current with the latest trends in semiconductor design, drive design innovations, providing technical leadership and mentoring within the Hardware engineering team. Participate in internal and external technical forums and drive a culture of innovation

Other Responsibilities:

Perform all activities in a safe and responsible manner and support all Environmental, Health, Safety & Security requirements and programs.

Required Qualifications: 

• Master’s degree or higher in Electrical Engineering, Mechanical Engineering, Computer Science, or a related field. 

• Minimum 10+ years of experience of relevant semi-conductor experience with package co-design or package design. Minimum 5+ years of experience with proven demonstrated on co-design for complex SoC design and working on high-speed or high-power or heterogeneous systems. Proven expertise across different package technologies is required

• Strong understanding of different package technologies such as Flip-chip, WLCSP, FCBGA, wire-bond and advanced package technologies such as 2.5D, 3D, interposers and chiplets

• Working knowledge and understanding of industry-standard EDA tools for package and board level simulations such as Cadence, Synopsys, Ansys, HFSS etc. Understanding of tools for PDN design and IO ring planning tools from Cadence and Synopsys

• Strong understanding of manufacturing flows, yield considerations and reliability standards esp. related to Automotive

• Excellent communication and documentation skills: Capable of producing clear, comprehensive requirements and architecture and design documentation for both internal and external usage 

• Collaborative mindset: Comfortable working in global, cross-disciplinary teams and engaging directly with customers and partners 

Preferred Qualifications:

• Experience in prior ASIC or SoC designs covering mixed-signal Analog, high-speed interfaces, networking highly preferred

• Experience engaging and driving foundry and OSAT partners and exposure to GF technology nodes highly preferred

• Contributions to Industry relevant standards, track record of patents or publications in technical conferences or industry presentations highly desired