The Role:
Lead the global, mission-critical infrastructure that powers Cadence's EDA tools development, enables customers to design and verify the world's most advanced semiconductors faster and more reliably. This strategic leadership role combines deep Enterprise IT expertise with strong knowledge of the semiconductor design lifecycle—from concept through verification and signoff.
High‑Performance EDA Infrastructure
Architect, scale, and operate large‑scale Linux/Unix compute environments optimized for high‑concurrency simulation, regression, and verification workloads.
Deliver low‑latency, high‑throughput storage solutions tuned to the unique I/O demands of analog, digital, and mixed‑signal EDA tools.
Oversee global data centers and execute a hybrid cloud strategy that enables seamless capacity bursting during peak design, verification, and emulation cycles.
Lead and develop global Linux/Unix engineering teams responsible for platform stability, performance optimization, and availability across Cadence’s full EDA tool suite.
Define and execute WAN and campus LAN strategies, VPNs, and Zero Trust security models to safeguard sensitive semiconductor IP.
Own backup, recovery, and disaster‑resilience capabilities to ensure business continuity for mission‑critical environments.
Maintain compliance with global cybersecurity, data sovereignty, and risk‑management standards.
EDA Ecosystem & Strategic Partnership
Partner closely with EDA R&D leaders to align infrastructure roadmaps with next‑generation analog, digital, mixed‑signal, verification, and emulation technologies.
Support specialized data‑center environments for hardware emulation platforms, including high‑density compute, advanced networking, and low‑latency interconnects.
Lead the delivery and ongoing operation of Cadence Cloud infrastructure from owned data centers and co‑location facilities.
Monitor industry and technology trends across HPC, cloud, networking, and storage to keep Cadence’s infrastructure ahead of customer and market demands.
Communicate infrastructure strategy, risks, and business impact effectively to senior technical leaders and executives.
Qualifications
15+ years of leadership experience in IT infrastructure within semiconductor, EDA, HPC, or large‑scale R&D environments.
Expert‑level knowledge of Linux/Unix systems, high‑performance networking, and enterprise‑class storage architectures.
Deep understanding of semiconductor design flows, including RTL‑to‑GDSII, verification, and emulation.
Proven ability to lead global teams and manage complex, mission‑critical platforms at scale.
Strong communication skills, with the ability to translate technical strategy into clear business value for executive audiences.
Bachelor’s degree in Computer Science, Electrical Engineering, or a related field; advanced degree preferred
The annual salary range for California is $185,500 to $344,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.
cadence