Job Details:
Job Description:
- Part of the global PCIe/CXL Center of Excellent (CoE) team, developing the latest & state of the art PCIe/CXL solution for next generation FPGA in the latest process technology node.
- Develops the logic design, register transfer level (RTL) coding, and simulation for FPGAs to generate cell libraries, functional units, IP blocks, and subsystems for integration in full chip designs.
- Participates in the definition of PCIe/CXL architecture and microarchitecture features of the block being designed. Works with IP providers to integrate and validate IPs at the SoC level.
- Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation.
- Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features.
- Performs quality checks in various logic design aspects ranging from RTL to timing/power convergence. Drives quality assurance compliance for smooth IP/SoC handoff.
Qualifications:
- Bachelor degree in Electrical, Electronics, Computer Engineering or equivalent.
- Experienced in FPGA, custom IC or ASIC design and verification, demonstrated excellence in any of the product development areas from architecture, design, validation to product.
- 10+ years of experience in RTL design with Verilog and VHDL.
- Familiar of logic simulations and design verification.
- Knowledge of PCIe is a strong plus.
- Familiarity with Python, Perl, TCL and shell scripts is a plus.
- Highly motivated to learn and adapt to fast changing technologies and environments.
- Exceptional analytical, problem solving and communication skills, initiative, promote innovation and teamwork.
- Self motivated and ability to excel in a team environment.
- Demonstrates fundamental values such as accountability, integrity and a winning mindset.
Job Type:
Regular
Shift:
Shift 1 (Malaysia)
Primary Location:
Penang 15, Penang, Malaysia
Additional Locations:
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.