The job opening is for a full-time Research Staff Member in the Design Group in Western Digital's research department. The role will be a part of a multi-functional team whose aim is to develop and eventually commercialize Western Digital's strategic radiation hardened memory technology.
The responsibilities for the role will include:
- Developing high density memory chip custom layout
- Including shared operational circuitry along with at pitch line drivers
- All phases of chip design layout to be included: From architecture definition, density and performance optimization, final verification up to and including tape out
- Running and Debugging Physical Verification flows including DRC, LVS, ERC and Antenna Checks
- Minimize parasitic resistance and capacitance (R and C) in critical paths to meet timing and power consumption specifications
- Comprehend and address reliability engineering issues such as electromigration, IR Drop and Design For Manufacturing robustness
- Coordination of a Split-Fab Design and Development between WD (for Memory Array Layers) and a CMOS Foundry (for Operational Circuitry)
- Developing and Harmonizing CMOS Foundry wafer requirements to allow for continued processing of Memory Array layers in WD鈥檚 Fabrication Line
- Development of EDA Tool Design Rules for WD鈥檚 Memory Array Layers
- Defining and executing the split-fab tape out flow