Define and drive Architecture of the chiplets optimized for MCU constraints
Define and drive Architecture of the D2D interface IPs targeted for MCU chiplets
Collaborate closely with product and software architects to define and refine the architecture
Play a key role in shaping the microarchitecture of the IP blocks and the subsystems
Work closely with functional verification teams on test-plan development and reviews
Collaborate with other functional teams including Design, Validation, DFT, physical design and emulation teams to achieve architectural goals and performance targets
Provide support to functional validation teams in post silicon debug
IP selection and make/buy decisions are a key factor for this role