Sr. Engineer, Design Enablement

We’re looking for a Senior Engineer (5+ Years) in design enablement space, with strong RTL and static verification expertise to help build robust design-quality methodologies across our teams.

Key Skills

• Strong RTL design experience (Verilog/SystemVerilog)
• Strong hands-on knowledge of Lint, CDC, RDC flows
• Tcl and shell scripting 
• Python (good to have)
• Ability to debug RTL/static issues and improve design quality