We are seeking a highly experienced Senior Staff RTL Design Engineer to join our SoC development team. This role involves RTL design for chiplet based power efficient chips and collaborating across architecture, verification, and physical design teams to deliver world-class semiconductor solutions.
Job Summary
- Design and implement RTL for IPs and chip level using Verilog/SystemVerilog and industry-standard methodologies
- Optimize RTL for timing, power, and area targets while ensuring design scalability
- Work closely with architecture, firmware, and physical design teams during development and implementation
- Collaborate with verification teams to ensure functional correctness and coverage goals
- Work closely with synthesis and physical design teams for PPA analysis and convergence
- Work with DFT teams to achieve coverage goals
- Contribute to methodology improvements for design implementation and timing closure
- Provide technical leadership and guidance to junior engineers
- Provide support to functional validation teams in post silicon debug