Senior Staff Design Architecture Engineer

What you’ll do

• Architect and optimize digital multiphase voltage regulators.
• Perform gain/phase margin and stability analysis; architect and design robust loop compensation.
• Model and simulate regulator behavior (steady‑state & transients) in Simplis/MATLAB/Simulink/SystemVerilog.
• Define PWM modulation, phase‑management, current sensing, and ripple minimization strategies.
• Model/Implement/verify control logic with SystemVerilog/Verilog; collaborate across analog, digital, and mixed‑signal teams.
• Validate designs via small‑signal and time‑domain analysis; drive improvements to feedback systems.

What you’ll bring

• Deep understanding of feedback control, Bode/Nyquist, and stability criteria.
• Strong DSP fundamentals applied to digital power control.
• Proven modeling skills: behavioral, small‑signal, and system‑level.
• Hands‑on with multiphase converters, PWM schemes, current‑balance, and transient optimization.
• SystemVerilog/Verilog proficiency for RTL design and verification (UVM a plus).
• Scripting in MATLAB/Python preferred.