Job Summary
We are seeking an experienced and strategic Sr Test Engineer to lead our test engineering initiatives in Hukou location. The ideal candidate will not only possess expert-level skills in ATE test program development but also drive test strategy, DfT (Design for Testability) implementation, and technical mentorship for the team.
Key Responsibilities
- Test Architecture & Strategy: Define and architect cost-effective and high-efficiency test solutions for Gate drivers, Power Stages and Isolators products on Cohu DMDx, DMDx DxV and Acco STS8300 platforms.
- Advanced Hardware Engineering: Lead the design reviews of complex high-performance test interface hardware (Load board, Probe Card). Solve signal integrity and thermal challenges for high-voltage/high-power (GaN) applications.
- NPI Test Leadership: Drive test build for NPI projects from concept to release. Drive DfT (Design for Testability) discussions with IC Design teams during the pre-silicon phase to ensure test coverage and yield targets. Also, together with Silicon Validation team, achieve characterization completion by ATE portion.
- Yield & Cost Optimization: Drive systematic yield improvement through advanced statistical data analysis. Formulate and execute aggressive Test Time Reduction (TTR) strategies to significantly lower the Cost of Test (CoT).
- Excellent communication, teamwork, and interpersonal skills, act as the technical focal point for cross-functional collaboration with international Designer, PE, and OSATs.