We are seeking a highly skilled Staff Digital Design Engineer to join our Memory Interface Devices (MID) Business Unit. In this role, you will lead the micro-architecture and design of highâperformance chips for nextâgeneration memory interface products. You will collaborate closely with crossâfunctional teamsâincluding analog/mixedâsignal, architecture, verification, and validationâto deliver robust, powerâefficient, and highâthroughput memory interface solutions.
This position is ideal for an engineer with deep expertise in DDR and LPDDR memory technologies and a strong background in complex digital logic design.
Key Responsibilities
- Lead RTL design and microâarchitecture development for memory interface digital blocks and subsystems.
- Own endâtoâend design flow: specification â microarchitecture â RTL coding â work with PnR team on timing closure â debug â release.
- Drive design reviews, documentation, and design quality best practices across the BU.
- Collaborate with analog/mixed-signal teams for coâdesign of PHY and controller components.
- Partner with verification teams to define verification plans, corner-case scenarios, and coverage goals.
- Perform synthesis, linting, CDC, RDC analysis, and support physical design for timing and power closure.
- Support silicon bring-up, debug, characterization, and postâsilicon validation teams.
- Contribute to technical strategy, innovation, and roadmap definition for next-gen memory interface products.
- Mentor junior engineers and influence engineering best practices across the organization.