Staff Digital Engineer

We are seeking a highly skilled Staff Digital Design Engineer to join our Memory Interface Devices (MID) Business Unit. In this role, you will lead the micro-architecture and design of high‑performance chips for next‑generation memory interface products. You will collaborate closely with cross‑functional teams—including analog/mixed‑signal, architecture, verification, and validation—to deliver robust, power‑efficient, and high‑throughput memory interface solutions.

This position is ideal for an engineer with deep expertise in DDR and LPDDR memory technologies and a strong background in complex digital logic design. 

Key Responsibilities

• Lead RTL design and micro‑architecture development for memory interface digital blocks and subsystems.
• Own end‑to‑end design flow: specification → microarchitecture → RTL coding → work with PnR team on timing closure → debug → release.
• Drive design reviews, documentation, and design quality best practices across the BU.
• Collaborate with analog/mixed-signal teams for co‑design of PHY and controller components.
• Partner with verification teams to define verification plans, corner-case scenarios, and coverage goals.
• Perform synthesis, linting, CDC, RDC analysis, and support physical design for timing and power closure.
• Support silicon bring-up, debug, characterization, and post‑silicon validation teams.
• Contribute to technical strategy, innovation, and roadmap definition for next-gen memory interface products.
• Mentor junior engineers and influence engineering best practices across the organization.