Senior Analog Design Engineer

Individual Contributor role for Technical leader with 2-5 years of experience in Analog and Power IC development within 2.6B$ Power Business Unit at Renesas. Primary responsibilities include leading the IP design blocks for development of power management ICs, including voltage regulators, power converters, and other related components and collaborate with cross-functional teams to ensure successful integration of ICs into larger systems. The candidate will work on a wide range of exciting and cutting edge PMICs, including Linear and Switching DC-DC converters powering the next generation of most sought-after phones and handheld devices. This is an early-stage growth opportunity where in the candidate will get to learn, build and over time contribute and influence the charter for Renesas’s massive Power product portfolio. This is an IC role with complete focus on product development and no people management.

Essential Functions:

· Identify and resolve technical challenges and risks.

· Should have a very good understanding of Power devices, operations and design trade-offs for better performance & reliability.

· Should be able to lead development and integration of complex I/Ps like +ve/-ve Charge Pumps, Source-Sink LDOs, Ultra-low power Oscillators (including Relaxation type), Temperature Sensor, Current Sense, SAR ADCs, House Keeping blocks, Protection (Thermal, Under-Voltage, Over-Voltage, Over Current etc) and other analog blocks including Bandgap references, V2I, Analog Buffers, Op-Amps, Comparators, High speed level shifters etc. Thorough understanding of Switch Cap circuits is a must.

· Must have in-depth understanding of and should be able to choose, design & compensate Control loops keeping in mind the target performance.

· Must be able to bring in innovative ideas to improve designs to meet challenging specifications and achieve better system performance.

· Should have in-depth knowledge of Analog layouts, FET layouts, Noise isolation techniques and be able to guide the layout development from floor planning till Chip Top completion and verification and do trade-offs based on desired performance.

· Must be conversant with the standard design, extraction and simulation flows & tools, speed, convergence, accuracy trade-offs and should be able to optimize setups based on Pre/Post (with/without) Parasitic using simulator options, debug and navigate through tool related challenges.

· Should be able to setup design flows and methodologies including checklists, reviews to ensure quality designs and take them all the way to Silicon success.

Qualifications

Minimum Requirements:

· Bachelor’s or master’s degree in electrical engineering

· 2-5 years in Analog Circuit Design.

· Solid understanding and design experience of complex analog designs with full ownership.

· Willingness to explore and learn.

· Willingness to take ownership and take tasks at hand to completion.