Principal Design Verification Engineer

We are seeking a highly experienced MCU Design Verification Principal Engineer to lead and contribute to the verification of complex MCU / SoC designs. In this role, you will take technical ownership of verification strategy, methodology, and execution to ensure functionality, performance, and quality meet project and customer specifications.
This position requires deep expertise in MCU architecture, advanced verification methodologies, strong technical leadership, and the ability to collaborate effectively with global cross‑functional teams.

Key Responsibilities

Verification Planning & Strategy:
Define and own end‑to‑end verification strategy for MCU / SoC at IP, subsystem, and full‑chip levels.
Develop and maintain verification plans based on SRD / PRD / architecture specifications.
Define verification metrics and sign‑off criteria, ensuring coverage‑driven verification completeness.

Testbench & Environment Development:
Architect, review, and enhance scalable and reusable verification environments using SystemVerilog and UVM.
Lead development of test infrastructure including drivers, monitors, scoreboards, assertions, and coverage models.
Promote best practices for reuse across MCU projects.

Debugging, Analysis & Quality Assurance:
Lead debugging and root‑cause analysis of complex functional, integration, and low‑power issues.
Work closely with RTL, architecture, and backend teams to ensure early issue detection and resolution.
Drive functional and code coverage closure to meet project quality targets.

Methodology, Automation & Productivity:
Drive continuous improvement of verification methodologies, including constrained‑random, assertion‑based, and formal verification.
Contribute to verification flow standardization across projects.

Technical Leadership & Mentoring:
Act as technical lead and sign‑off owner for assigned IPs, subsystems, or chip‑level verification.
Mentor and coach verification engineers, providing technical guidance and best practices.
Collaborate with global teams (VN / JP / IN) in a multi‑site development environment.