We are seeking a Principal/Sr. Principal RISC-V CPU Architect with 10 to 15 years of experience to lead the architecture, development, and assessment of next-generation RISC-V processor cores. The ideal candidate will have deep expertise in high-performance CPU micro-architecture and a comprehensive understanding of the RISC-V and thorough understanding of Micro controller and micro processor architecture.
Responsibilities:
- Core Architecture & Specification: Define and develop detailed micro-architecture specifications for RISC-V units, including branch predictors, rename logic, instruction scheduling, and vector execution.
- Design & Development: Lead the RTL development of CPU cores, ensuring alignment with power, performance, area (PPA), and timing goals.
- Assessment & Benchmarking: Evaluate and benchmark various RISC-V core implementations (in-order vs. out-of-order, superscalar) against target workloads and performance models.
- Virtualization & Security: Implement and optimize hardware-assisted virtualization features and architectural extensions for secure execution environments.
- Infrastructure & Fabric: Architect and integrate critical infrastructure elements, including Bus fabrics (e.g., CHI, AXI), clocking, reset logic, and power management subsystems.
- Full Design Flow Management: Oversee the complete design lifecycle from architectural exploration to physical design delivery, including functional and performance verification.