Experience: 10-15 years
Role Summary
We are seeking Physical Design expert/manager with strong people and technical skills in Synthesis, UPF, VCLP, LEC to join our semiconductor backend team. The role focuses on RTL synthesis ownership, LEC closure, UPF development, and VCLP sign鈥憃ff for complex SoC designs, working closely with Physical Design, DFT, and Front鈥慐nd teams. The person should have skillset for people management as well.
Key Responsibilities
- Complete understanding of RTL to GDS flow in physical design cycle.
- Able to collaborate, lead and drive team members with quality and schedule in check, aligned to organizational needs.
- Own RTL synthesis from elaboration to final signoff.
- Debug design constraints and support DFT insertion. Cross team collaboration is must.
- Ability to handle multiple tasks (at individual and at team level) and changing priorities from internal customers.
- Deep debug skillset for logic equivalence checks (LEC) across RTL, synthesized, and ECO netlists.
- Create, maintain, and debug UPF, ensuring alignment with FE power intent.
- Understand, Define and manage power domains (power switches, isolation, retention, alwayson). Support lowpower signoff (VCLP / power checks).
- Handle RTL ECOs during late design stages.
- Automate flows using TCL scripting.
- Lead by example technically by having a strong technical expertise in several areas of Physical Design.