Altera is looking for a talented and driven Director – Pre-Silicon Verification (IP Development) to lead and inspire a multidisciplinary team. In this critical role, you will manage design engineers across multiple functional domains. You’ll be at the forefront of Altera’s product innovation, driving high-quality silicon solutions that meet power, performance, area, and cost objectives.
Key Responsibilities:
1. Lead pre-silicon verification strategy and execution for IP development.
2. Develops FPGA verification plans, test benches, and the verification environment to ensure coverage to confirm to microarchitecture specifications.
3. Executes verification plans and defines and runs system simulation models to verify the FPGA design, analyze power and timing, and uncover bugs.
4. Replicates, root causes, and debugs issues in the pre-silicon environment.
5. Finds and implements corrective measures to resolve failing tests.
6. Documents, reviews, and executes the verification strategy plan on different methodologies/techniques (e.g., gate-level-simulation strategy, power patterns/aware simulations) used to enable feature coverage as per the microarchitecture specifications.
7. Developing validation test suites and driving continuous improvement into existing validation test suites and methodologies.
8. Complete verification life cycle (verification architecture, test plan, execution, debug, coverage closure).
1. B.Tech/M.Tech/M.S. in Electrical Engineering, Electronics, or related field.
2. Ph.D. preferred but not mandatory.
3. Related technical experience should be in/with: Pre Silicon Validation/Verification.
4. OVM/UVM, System Verilog, constrained random verification methodologies.
Preferred Qualifications:
1. Experience in design Verification with developing, maintaining, and executing complex IPs and/or SOCs.
2. Experience in FPGA architecture or FPGA prototyping
3. This role is for Hyderabad (remote until future onsite)
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