Develops the logic design, register transfer level (RTL) coding, and simulation for Network on Chip IPs and potentially other FPGA IPs & subsystem for integration in full chip designs.
Participates in the definition of architecture and microarchitecture features of the block being designed.
Creates prototypes, simulates models, and specifies systems requirements.
Prepares and designs logic diagrams and codes for implementing system design and test specifications.
Delivers software models for device level bring up, including user visible functionality, timing, and power.
Applies RTL implementation techniques to qualify the design to meet required power, performance, and area goals, partnering with physical implementation team.
Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features.
As a senior designer of the team, you're also expected to groom next level technical members, technically oversee & guide the entire NOC team as well as proactively anticipate potential design challenges & roadblocks and take mitigation actions to ensure the successful execution of the SS that meets the requirement of the project & schedule.
Bachelor's or Master's Degree in Electrical Engineering, Computer Engineering, or a related field with 15+ years of related working experience.
Experience in System Verilog, VCS/Synopsys simulators, Lint and Synthesis
Experience in programming with C/C++/Perl/Python/TCL/Unix Shell script
Experience in FPGA design and programming is a plus.
Experience in RTL validation is a plus.
Experience in development of Network on Chip IPs.
Ability to work with different teams, good communication and problem-solving skills.
altera