Validates and researches the Quartus Synthesis & Compiler optimizations, Partial Reconfiguration (PR) flow, Debugging features like SignalTap using Quartus Design Software and Altera FPGA Hardware.
Creates Altera device-specific testcases with Verilog/VHDL and Altera IPs and verifies them for timing & functionality using industry-standard simulation and formal verification tools.
Regresses the designs during each release for QoR, and monitors performance over the targeted FPGAs to assess improvements.
Collaborates with cross-functional teams to develop and improve Synthesis & Compiler test coverage and helps resolve customer issues as they occur.
Experience : Min. 5+ yearsof relevant experience in FPGA/ASIC RTL Design, verification and HW Debug.
Education : Master's/Bachelor's Degree in Electronics/VLSI/Digital Design or other related disciplines.
Requirements -
FPGA/Digital Logic Design, RTL design and verification using VHDL, Verilog or SystemVerilog.
Experienced in FPGA Devices like Agilex, Virtex and Tools like Altera Quartus, Xilinx Vivado, Synplify, etc
Good experience in FPGA Partial Reconfiguration (PR) flow, and HW debugging skills using SignalTap or ChipScope.
Good experience with Simulation/Verification of digital designs using VCS, Questa, XCelium, Timing Analysis (STA) and Hardware validation of FPGA Designs.
Knowledge of at least one of Shell, Perl, TCL or Python Scripting is essential.
Knowledge of AHB, AXI, PCIe, Ethernet, Avalon bus protocols, and High-Speed interfaces is essential
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